CMOS technology is conventionally used to implement digital integrated circuits. Often CMOS circuits drive large capacitive loads. Such capacitive loads may occur due to on-chip interconnections, output pads, or off-chip loads. The CMOS circuit commonly used for driving large capacitive loads is the tapered buffer. A typical digital three stage tapered buffer or amplifier chain is shown in FIG. 1. An input data signal Vin is amplified by the three CMOS inverter stages to the final output node Vout. Each of the stages of the buffer circuit consists of a PMOS pull-up transistor P coupled to the high potential power rail V.sub.dd, an NMOS pull-down transistor N coupled to the low potential power rail GND, an input terminal that connects the gates of the N and P transistors, and an output terminal between the P and N transistors connected to the input terminal of the next stage.
A transition from logic 1 (high) to logic 0 (low) at the input of any stage of the tapered buffer turns off the N transistor and turns on the P transistor of that stage, producing a transition from low to high at the output terminal of the respective stage. Similarly, a transition from low to high at the input of any stage of the tapered buffer turns on the N transistor and turns off the P transistor of that stage, producing a transition from high to low at the output terminal of the respective stage.
As shown in FIG. 1, the output of the first stage O1 drives the capacitive load that consists of the gate capacitances of the transistors P2 and N2 of the second stage, the output of the second stage O2 drives the capacitive load that consists in the gate capacitances of the transistors P3 and N3 of the third stage, and the output of the third stage Out drives the load capacitance C.sub.L. The other parasitic capacitances, such as the junction capacitances, are ignored for this discussion, since for a typical tapered buffer sizing they are much smaller than the gate capacitances.
Each stage of this amplifier chain introduces a delay in the data signal propagation from the tapered buffer input to the tapered buffer output. A first order equation for the delay introduced by any stage of the tapered buffer is ##EQU1##
s where t is the delay introduced by the stage, C is the capacitive load driven by the respective stage, V is the output voltage transition, and I is the current that charges (or discharges) the capacitive load C. The delay increases as the capacitive load C increases and decreases as the current I increases. For a logic family (for example a 5 V logic family), V is fixed. The current I increases as the transistor size increases, according to MOS transistor equations. However, the gate capacitance increases as the transistor size increases, also in a linear fashion. In order to obtain the same delay for the low to high (charging the load capacitor C) and high to low (discharging the load capacitor C) transitions of the output, the P and N transistors respectively of each stage must provide the same charging (or discharging) current I or the P and N transistors must have the same transconductance. Conventionally, to obtain the same transconductance for the N and P transistors of each stage of the tapered buffer involves sizing the P transistor three times the size of the N transistor of the respective stage.
The total delay introduced in the data path by a tapered buffer depends on the capacitive load C.sub.L that needs to be driven by the tapered buffer. Increasing the size of a stage of the tapered buffer decreases the delay introduced by that stage, but increases the gate capacitance of the constituent P and N transistors, and accordingly the capacitive load the stage represents for the previous stage, slowing down the previous stage. Also, since each stage of the tapered buffer introduces a delay, the total delay of the tapered buffer depends on the number of stages of the tapered buffer. For a given capacitive load C.sub.L that needs to be driven by a tapered buffer, an optimum exists so that the tapered buffer has minimum number of stages and introduces minimum delay. This optimum also provides the optimal sizing of each stage of the tapered buffer. According to this optimum, each stage of the tapered buffer is typically progressively increased in size by an optimal coefficient, each stage progressively providing higher amplification for the data signal (and higher charge/discharge current). The optimal coefficient is demonstrated to be e=2.713. For simplification of the following discussions, this optimal coefficient is considered equal to 3. Conventionally, the optimal coefficient is between 2.5 and 4.
According to the above, depending on the technology, the optimal transistor sizing and the internal capacitances at the internal nodes of the tapered buffer of FIG. 1 is: N1=1u, P1=3u, N2=3u, P2=9u, N3=9u, P3=27u, C.sub.in =c, C.sub.o1 =3c, and C.sub.o2 =9c, where u and c are relative units for size and capacitance. For an optimal design, the delay introduced by any stage is equal to the delay introduced by any other stage. For the tapered buffer in FIG. 1, this would mean that the delay of stage 1 is equal to the delay of stage 2, and is equal to the delay of stage 3. Accordingly, the total delay of an optimal tapered buffer is 3 (or n) times the delay of any stage.
For each stage of an optimal tapered buffer besides the last stage, for a low to high input transition of that stage, the output of that stage has to drive the gate capacitance of the N transistor of the next stage which is parasitic. The capacitance of the N transistor for this transition represents 25% of the total capacitance present at the output of a stage. For a high to low input transition of that stage, the output of that stage has to drive the gate capacitance of the P transistor of the next stage which is parasitic. The capacitance of the P transistor for this transition represents 75% of the total capacitance present at the output of a stage. According to Equation 1, the delay introduced by any stage of an optimal tapered buffer is 25% larger for a low to high input transition of that stage, and is 75% larger for a high to low input transition of that stage.
In addition, the parasitic capacitances of the N and P transistors of each stage of an optimal tapered buffer under the conditions described above have major influence on the dissipated power of the tapered buffer. Since the transconductances of the N and P transistors of any stage are often designed to be equal, during the transition of the input signal of each stage, when both N and P transistors are on, short-circuit current surges from V.sub.dd to ground (GND) through the two transistors, producing a parasitic short-circuit power. Also, the dynamic power dissipated by any one stage, is EQU P=CV.sup.2 f (2)
where C is the capacitance at the output node of the respective stage, V is the operating voltage of the circuit, and f is the switching frequency of the respective node, which increases as the capacitance C at that node increases. Accordingly, due to the parasitic N and P transistors under the conditions described above, any stage dissipates 25% more dynamic power for the low to high input transition of that stage, and 75% more dynamic power for the high to low input transition of that stage. Thus, it would be desirable to provide a buffer circuit which does not have the performance disadvantages in terms of delay, power dissipation, and parasitic short-circuit power loss of the tapered buffer circuit.
U.S. Pat. No. 5,061,864 describes the digital buffer circuits shown in FIGS. 2 and 3, and the mono-phase logic concept. In both FIGS. 2 and 3, the upper path drives the P4 transistor for a low to high input transition of the buffer producing a low to high output transition of the buffer, and the lower path drives the N4 transistor for a high to low input transition of the buffer, producing a high to low output transition of the buffer. In FIG. 2, the following is provided: a relatively higher speed output pull-up turn on signal propagation path consisting of transistors N1U, P2U, N3U, and P4, called herein UO, a relatively higher speed output pull-down turn on signal propagation path consisting of transistors P1D, N2D, P3D, and N4, called herein DO, a relatively slower speed output pull-down turn off signal propagation path to turn off the final pull-down transistor N4 consisting of transistors N1D, P2D, and N3D, called herein DOF, and a relatively slower speed output pull-up turn off signal propagation path to turn off the final pull-up transistor P4 consisting of transistors P1U, N2U, and P3U, called herein UOF. To avoid or reduce the crowbar current between transistors N4 and P4, a negative feedback circuit arrangement is provided in the buffer of FIG. 3 consisting of GNA and GNO logic gates that replaces inverter I1U and I1D of FIG. 2, and a data saver circuit consisting of inverters IF5 and IF6 for saving the output data signal after turn off of both transistors N4 and P4.
Consider D, the delay of the buffer of FIG. 3 when the input signal has a waveform as illustrated in FIG. 4. Between any two input transitions there are kD time units, where k is greater or equal to 1. Consider a low to high input transition of the buffer, the signal propagates through UO and produces a low to high output transition after a delay D. The output, in the final high state, through inverter IF5 in the feedback path, turns off UO and turns on UOF. After kD time units, a high to low input transition of the buffer propagates through DO and produces a high to low output transition after a delay D. Transistor P4 must be off at the time the high to low input transition of the buffer turns on transistor N4 through DO. In other words, since UOF turns off transistor P4, UOF must turn off transistor P4 in approximately kD time units. A similar discussion can be made for DO and DOF.
The signal propagates through the relatively higher speed path (UO or DO) in D time units, while it is required to propagate through the relatively lower speed path (UOF or DOF) in approximately kD time units. Since for an optimal design each stage introduces the same delay, each of the four stages of the buffer shown in FIG. 3 introduces a delay equal to D/4 time units for the signal propagation. On the other hand, since transistors P4 and N4 are required to be turned off in kD time units, the time allocated for this procedure to each of the three transistors involved are approximately kD/3 time units. Considering inverter I2U in FIG. 3, if transistor P2U is of size S, the size of transistor N2U for a stage in a tapered buffer of FIG. 1 would be S/3. However, since for the buffer in FIG. 3, transistors P2U and N2U are required to provide different transconductances according to Equation 1, if transistor P2U is of size S, transistor N2U must be ##EQU2##
Similarly for inverter I3U of FIG. 3, if transistor N3U is of size S1, the size of transistor P3U for a stage in a tapered buffer of FIG. 1 would be 3S1. However, since for the buffer in FIG. 3, transistors N3U and P3U are required to provide different transconductances, then according to Equation 1, if transistor N3U is of size S1, transistor P3U must be ##EQU3##
In Equations 3 and 4, for large k (small frequencies), transistors N2U and P3U are much smaller than the corresponding sizes for a tapered buffer of FIG. 1, and similarly for all other similar transistors. Gate GNA, and inverters I2U and I3U represent a tapered buffer as in FIG. 1, specially sized according to the requirements of the buffer from FIG. 3. For this specially sized tapered buffer, and for small frequencies, transistors N2U and P3U discussed herein represent a minimal, negligible overhead for delay and power as described for the tapered buffer of FIG. 1. Accordingly, the output of each stage of this specially sized tapered buffer drives for small frequencies minimal (negligible) parasitic capacitances as discussed for the tapered buffer of FIG. 1. However, as the operation frequency increases, namely for small k values, transistors N2U and P3U sizes increase according to Equations 3 and 4. For large frequencies (k=1), transistors N2U and P3U sizes reach the sizes of the corresponding transistors in a tapered buffer according to FIG. 1. Accordingly, as the operation frequency increases, the chain of inverters from FIGS. 2 and 3 become similar to the chain of inverters in a tapered buffer of FIG. 1, presenting high parasitic capacitances discussed earlier, and thus experiences the performance degradation in delay and power dissipation similar to the tapered buffer. This means that the delay and power dissipation advantages of the buffer shown in FIGS. 2 and 3, which may be present at small frequencies, are absent at higher frequencies. The low or high frequency ranges of the buffer circuit depend on the particular technology used in the circuit, for example, for 1.2 micron-based semiconductors, high frequency may be 300 or 600 MHz and low frequency input signals may be 100 MHz or less. Thus, it would further be desirable to provide a buffer circuit capable of optimally transmitting data signals at higher speed and less dissipated power over any frequency of input data signals received by the buffer.